1. Field of the Invention
The present invention relates to a circuit substrate and a semiconductor package having the same, and more particularly to a common circuit substrate and a semiconductor package having the same.
2. Description of the Related Art
FIG. 1 shows a schematic top view of a first conventional circuit substrate applied to a memory card. The circuit substrate 1 includes an upper surface 11, a lower surface (not shown), a first layout area 12, and a second layout area 15. The first layout area 12 is located on the upper surface 11, and has a plurality of first electrical contacts 121 for carrying a memory chip 13 (for example, a flash IC). The first electrical contacts 121 surround the memory chip 13. The memory chip 13 is adhered to the first layout area 12, and has a plurality of first bonding pads 131. The first bonding pads 131 are electrically connected to the first electrical contacts 121 through a plurality of first wires 14.
The second layout area 15 is located on the upper surface 11 and below the first layout area 12, and has a plurality of second electrical contacts 151 for carrying a control chip 16. The second electrical contacts 151 are electrically connected to the first electrical contacts 121 through a first circuit (not shown). The control chip 16 is adhered to the second layout area 15, and has a plurality of second bonding pads 161. The second bonding pads 161 are electrically connected to the second electrical contacts 151 through a plurality of second wires 17.
A plurality of I/O pads (not shown) is disposed on an edge of the lower surface of the circuit substrate 1 for inputting/outputting an external signal. The I/O pads are electrically connected to the second electrical contacts 151 through a second circuit (not shown).
The circuit substrate 1 operates as follows. First, the second electrical contacts 151 and the second bonding pads 161 both can be divided into a first portion and a second portion. An external signal is input into the I/O pads and transmitted to the first portion of the second electrical contacts 151 through the second circuit. Then, the signal is transmitted to the first portion of the second bonding pads 161 of the control chip 16 through the second wires 17, so as to enter the control chip 16 and to be processed therein.
Afterward, the processed signal is output from the second portion of the second bonding pads 161 of the control chip 16, and then transmitted to the second portion of the second electrical contacts 151 through the second wires 17. Next, the signal is further transmitted to the first electrical contacts 121 of the first layout area 12 through the first circuit, and then to the first bonding pads 131 of the memory chip 13 through the first wires 14. Finally, the signal is stored in the memory chip 13.
When a signal is to be withdrawn from the memory chip 13, the signal is first transmitted from the first bonding pads 131 on the memory chip 13 to the first electrical contacts 121 through the first wires 14, and then transmitted to the second portion of the second electrical contacts 151 through the first circuit. Then, the signal is transmitted to the second portion of the second bonding pads 161 of the control chip 16 through the second wires 17, so as to enter the control chip 16 and to be processed therein.
Afterward, the processed signal is output from the first portion of the second bonding pads 161 of the control chip 16, and then transmitted to the first portion of the second electrical contacts 151 through the second wires 17. Next, the signal is further transmitted to the I/O pads through the second circuit, so as to be output externally.
FIG. 2 shows a schematic top view of a second conventional circuit substrate applied to a memory card. The circuit substrate 2 includes an upper surface 21, a lower surface (not shown), a first layout area 22, and a second layout area 25. The first layout area 22 is located on the upper surface 21, and has a plurality of first electrical contacts 221 for carrying a memory chip 23 (for example, a flash IC). The memory chip 23 has a plurality of first bonding pads 231, and the first bonding pads 231 are electrically connected to the first electrical contacts 221 through a plurality of first wires 24.
The second layout area 25 is located on the upper surface 21 and on the right side of the first layout area 22, and has a plurality of second electrical contacts 251 for carrying a control chip 26. The second electrical contacts 251 are electrically connected to the first electrical contacts 221 through a first circuit. The control chip 26 has a plurality of second bonding pads 261, and the second bonding pads 261 are electrically connected to the second electrical contacts 251 through a plurality of second wires 27.
A comparison of FIG. 1 and FIG. 2 shows that the size of the memory chip 13 differs from that of the memory chip 23, so the substrate layout is apparently different from each other and cannot be shared. In practice, there are many types of memory chips and control chips having different profiles that can be applied to the layout of the substrate of a conventional Micro SD Card (Micro Secure Digital (Memory) Card). Thus, when different devices are used together, since the space on the substrate is limited, the arrangement of the chips and the electrical contacts should vary accordingly. As a result, different substrate layout designs have to be adopted to meet different requirements (as shown in FIGS. 1 and 2). When preparing the substrate, there also have to be different types of substrate to meet the requirements of the production, which not only prolongs the manufacturing process, but also increases the design and manufacturing cost of the circuit substrate.
Therefore, it is necessary to provide an innovative and advanced circuit substrate to solve the above problems.